define LFDS710_PAL_ATOMIC_ISOLATION_IN_BYTES
Source File
└───liblfds710
└───inc
└───liblfds710
lfds710_porting_abstraction_layer_processor.h
Define
#define LFDS710_PAL_ATOMIC_ISOLATION_IN_BYTES [atomic isolation length in bytes]
Example
#define LFDS710_PAL_ATOMIC_ISOLATION_IN_BYTES 2048
Optionality
This define is mandatory and the library cannot compile if it is not set.
Notes
Atomic operations specify certain alignment requirements upon the variables in use - typically four byte alignment on 32 bit platforms, and 8 byte alignment on 64 bit platforms. However, the nature of memory and CPU caches are such that an atomic opertion makes the cache line holding the target exclusive for the processor performing the operation, and invalid for all other processors. Consequently, it is often desireable to pad variables used in atomic operations such that they have the cache line to themselves - otherwise, the other variables in the cache line will be adversely impacted by the invalidations inflicted upon them, and also it may be there are other atomic variables in the same cache line which should be wholly independent of each other but end up being entangled because whenever one of the experiences an operation, it affects the cache line status of all the others in that cache line.
However, the actual length of store needed to make a variable isolated with regard to atomic operations may be more than the length of a cache line. For example, by default on Intel, the processor when fetching a cache line always also fetches the following cache line. Another example is that of some of the LL/SC processors, such as ARM, which use Exclusive Reservation Grandule, which on ARM range from 8 to 2048 bytes in length.
As such, this define exists, and it is the length (and alignment) of store required for atomic isolation.
The value is usually the cache line length. On LL/SC with ERG, it is the larger of the cache line length and ERG length (i.e. if ERG is less than one cache line, we use the cache line length).
If this value is incorrectly set, the consequence is a reduction (possibly large or very large) in performance. Also, on platforms which use LL/SC and have an exclusive reservation granule (ARM and POWERPC), structure sizes can become very large, and unnecessarily so.