define LFDS700_PAL_BARRIER_PROCESSOR_STORE
Source File
└───liblfds700
└───inc
└───liblfds700
lfds700_lfds700_porting_abstraction_layer_compiler.h
Define
#define LFDS700_PAL_BARRIER_PROCESSOR_STORE [processor store barrier directive]
Example
#define LFDS700_PAL_BARRIER_PROCESSOR_STORE __atomic_thread_fence( __ATOMIC_REL )
Optionality
This define is mandatory and the library cannot compile if it is not set.
Notes
Processors typically are able to re-order the flow of instructions, where this re-ordering is only guaranteed to be valid within the context of a single thread; e.g. if thread A performs an operation and then raises a flag, where thread B is waiting on the flag, the processor will in its re-ordering only take into account that the behaviour of the thread being re-ordered remains valid, such that in this case we might see in thread A the flag being raised before the operation is performed, since the processor isn't taking into account that thread B is written on the assumption the flag will be raised after the operation.
Compilers typically offer a directive which acts as a processor store barrier, where a processor store barrier the prevents the processor re-ordering store operations below the barrier above the barrier and prevents the processor re-ordering store operations above the barrier to below the barrier.